The present invention relates to an information processing system, and more particularly to a game computer system processing both image and sound data.
In a computer system, a CPU and peripheral devices are connected with each other through control, address and data buses. The CPU is connected to a memory and I/O devices through memory and I/O buses, respectively. In such a system, the following instructions are repeated to transfer data from the memory to the I/O spaces (I/O devices) continuously:
READ DATA FROM MEMORY PA1 WRITE DATA TO I/O PA1 READ DATA FROM MEMORY PA1 WRITE DATA TO I/O PA1 NOP PA1 READ DATA FROM I/O PA1 NOP PA1 WRITE DATA TO MEMORY
In a general computer system, the following instruction for reading or writing is prepared after the current process has been completed.
A game computer system which works at a high speed includes a CPU that processes the following instruction while the current instruction is being in process, this process being known as a DMA (Direct Memory Access) function. According to this system, data to be transmitted are accumulated on the memory bus, because the I/O bus transmits data slower than the memory bus. As a result, the computer system can not perform pipeline processing normally.
Accordingly, in one type of conventional game computer system, timing for transmitting data is controlled by a user program with NOP (NO Operation) instructions. That is, the following program is used to transfer data from the memory to the I/O space:
In this case, the transmission timing is adjusted by the NOP instruction after the data are written into the I/O space.
The following program is used to transfer data from the I/O space to the memory:
According to the program, the data are transmitted from the CPU to the memory securely.
Recently, with development of high performance CPUs, peripheral devices must be accessed with exact timings which are controlled by a program.
Generally, in an information processing system, the configuration of a DRAM (dynamic random access memory) is different depending on the type of data to be processed and the capacity of the memory, that is, the DRAM is addressed for each 8 and 16 bits when 8 and 16 bit data are to be processed, respectively. Most conventional computer systems employ decode IC chips for generating addresses fitting a variety of memory configurations.
FIG. 1 shows a memory of 64K.times.2 chip type, according to a conventional computer system. When address information is supplied to a decode IC, corresponding data in the memory are accessed by the decode IC. According to this system, the decode IC is necessary and the memory configurations are limited, and therefore, it is difficult to access a variety of memories having different configurations.
The memory (DRAM) is composed of plural memory cells each composed of a transistor and a capacitor to decrease its cost and to increase its integration rate. The DRAM is accessed by an address multiplex system to decrease the size of the system, as shown in FIG. 2. In this system, address signals are supplied to address terminals by a time division system, as shown in FIG. 3.
The DRAM is accessed in a high speed access mode to increase the access speed. In this mode, a word line is selected in accordance with a row address to supply all data connected with the word line to corresponding sense amplifiers, and then one of the amplifiers is selected in accordance with a column address to obtain data to be accessed. After that, when the column address only is changed, data stored in another sense amplifier is accessed.
When data are read from a memory in a read cycle, the memory is accessed by repeating RAS (Row Addressing) and CAS (Column addressing) cycles alternately, the cycle being called an "MADR cycle," and the access system a "page mode access." According to this system, much data can not be accessed at a high speed, this problem being serious for graphic data processing that needs to treat much continuous data.
Accordingly, another type of conventional computer systems employs a cache memory managed directly by a CPU, as shown in FIG. 5. The cache memory stores data read from a DRAM, so that the CPU reads the data from the cache memory directly, not from the DRAM. If the cache memory stores no data to be accessed by the CPU, the CPU must accesses the DRAM. For that reason, the cache memory is necessary to store enough data.
According to the conventional system, however, it is difficult to debug the program, because the CPU points to addresses in the cache memory, not in the main memory (DRAM). It is difficult to find the locations of program errors. Further, the system needs an extra memory chip for the cache memory in addition to the main memory (DRAM), and therefore, the hardware becomes complicated in structure.
In the conventional computer system, when the CPU is connected to peripheral devices of different types of bit (width), data to be transmitted are adjusted in width by software. For instance, when data are transferred from an 8-bit device to a 16-bit device, eight zeros are added at the end of 8 bit data to be transferred, as shown in FIG. 6. On the other hand, when data are transferred from a 16-bit device to an 8-bit device, the 16 bit data are divided into two pieces of 8 bit data to be transferred, as shown in FIG. 7. According to the conventional system, a program (software) must be designed in consideration of the width of data to be transmitted.
In general, an area out of a memory space is not addressed, when an application program is designed in a high-level language, because the memory is treated with variables. On the other hand, in a system program or application program which is designed using a low-level language, such as an assembler language, an address out of the memory may be specified.
In the conventional system, if a nonexistent address space is addressed, an incomprehensible image is displayed on a CRT. For example, in a game computer system dealing with sound and image, a strange image is displayed on a screen if a nonexistent address of a memory is specified.
FIG. 8 shows a memory space of the conventional system. Generally, the memory space to be addressed by the CPU is different from a space (0000).sub.16 to (1000).sub.16 for the actual memory (DRAM) region. In the conventional system, when the program specifies an address (3000).sub.16, an address decoder (address IC chip) analyzes the address as being an address (1000).sub.16, because the decoder ignores the addresses over the upper boundary address (1000).sub.16, as shown in FIG. 9. Although no datum exists at address (3000).sub.16, the system judges as if predetermined data exist there.
According to the conventional system, however, when a strange image is displayed on the screen, it is difficult to find the error location, because a programmer tends to guess that proper image data might have some errors, and therefore, the error can not be found in the worst case. In more detail, when a nonexistent memory area is accidentally specified, other data or instruction is broken, and therefore, an error occurs when the data or instruction is later accessed. Although an exceptional error may stop the processing when the instruction is broken, the error portion can not be found in debugging, because the error is based on the wrong addressing.